The semiconductor industry continues to be faced with market demand for integrated circuits (ICs) with added functionality and higher performance. In an effort to reduce die footprint, integrate more transistors, and achieve higher performance, interconnect structures that can allow multi-tiered ICs are being actively studied. Breakthroughs in new levels of die-scale integration are being facilitated by advances in vertical interlayer interconnect technology. With this technology, referred to as three-dimensional (3D) integration, a traditional IC is divided into multiple layers, and these layers are connected by vertical interconnects.
In 3D ICs, through-silicon-vias (TSVs) are the most-commonly used interlayer interconnects. This technology has been transitioned to the marketplace. For example, the AMD Fiji chip includes multiple five-die stacks with TSVs running through them. TSV-based 3D ICs offer many benefits, e.g., shorter interconnects, less power consumption, and reduced die footprint. However, the keep-out-zone required for TSVs leads to significant area overhead. Moreover, the die alignment precision in TSV-based 3D integration is limited to 1 μm, which prevents further reduction of the 3D contact pitch. Finally, TSVs are subject to intrinsic mechanical stress.
In order to fully exploit the potential of 3D integration, monolithic 3D (M3D) technology is being advocated as an alternative to TSV-based 3D ICs. M3D integration involves sequential layer-by-layer fabrication. After the bottom layer is formed on a substrate, the top layer is fabricated over the bottom layer. The two layers are connected together using interlayer vias (ILVs), and external I/O pins can directly access both the bottom layer and the top layer. Since the top layer can be constructed over a thin silicon substrate of around 30 nm in thickness, ILVs are one to two orders of magnitude smaller than TSVs. In addition, extremely high alignment precision is achieved, e.g., in the range of 10 nanometers (nm).
In emerging M3D applications, such as 3D FPGAs and the sequential integration of sensors, the digital logic is fabricated on the bottom layer, and memory or silicon-based sensors are fabricated on the top layer. In addition, the most advanced technology node is used only for the bottom layer. For this reason, defects are more likely to occur in the bottom layer, hence this layer must be tested carefully in order to ensure effective defect screening. In TSV-based 3D ICs, especially for die-to-die integration, the bottom die can be tested before it is bonded to other dies. However, in monolithic 3D ICs, the bottom layer cannot be tested until both layers are fabricated and I/O pads are available. It would be beneficial to provide the ability to test the bottom layer separately to enable defect isolation and yield enhancement.